The BrainStem architecture is meant to provide a standardized interface between conventional computer hardware such as personal computers and PDAs and the real-world needs of robots including motor control, sensor inputs, and other specific hardware.
This architecture is cross-platform allowing development in rich computer environments and actual implementation on any platform. In addition, since this is a standard and is cross-platform, higher level software constructs, algorithms, and development can immediately benefit all platforms.
This standard is meant to be open. The inter-module communication is handled using the industry standard IIC bus at 1 Mbit/sec. This allows many LCD displays, compasses, EEPROM memories, and other deviced to immediately be used in a BrainStem® enabled robot. Third-party developers are encouraged to consider supporting the BrainStem® protocol to take advantage of the software and communication layers in place.